In general, a sense amplifier is required to decode a specific cell of a memory cell array. This sense amplifier senses ON ("0" data)/OFF ("1" data) of the selected cell selected by X-decoder (bit line) and Y-decoder (bit line). An output buffer is employed to transmit the output of the sense amplifier to the next terminal.
As illustrated in FIG. 1, a general semiconductor memory device has: an X-decoder part 2 connected to a cell array part 1 and a word line of each cell, for applying the signal; a Y-decoder part 3 connected to the bit line of each cell, for determining if the data stored in the cell is output; a sense amplifier 4 connected to the bit line of each cell, for sensing the data of the selected cell; and an output buffer part 5 connected to the output terminal of the sense amplifier 4. Here, the output buffer 5 is for outputting the data of the cell sensed by the sense amplifier 4.
As illustrated in FIG. 2, a sense amplifier of a conventional semiconductor memory device includes first and second PMOS transistors 21, 22 to which a power supply Vdd and drain are connected; a first NMOS transistor 23 having a drain connected to the source of the second PMOS transistor 22 and a source connected to the bit line; and a second NMOS transistor 24 having a drain connected to the source of the first PMOS transistor 21 and a gate connected to the bit line. Here, the gate of the first NMOS transistor 23 is branch-connected to the source of the first PMOS transistor 21. The gates of the first and second PMOS transistors 21 and 22 are commonly connected to the Vss terminal. The output buffer 5 for outputting the data of the cell sensed by the sense amplifier is formed at the output terminal of the sense amplifier.
The operation of the thus-structured semiconductor memory device is as follows.
As illustrated in FIG. 1, if an address signal for selecting a specific cell is input to the X-decoder part 2 and Y-decoder part 3, the cell corresponding to the address signal is selected. For example, if a random cell C1 of the memory cell array 1 is selected and its data value is "1", C1 is turned off and the potential of the node K1 (which is the input terminal of the sense amplifier 4) is at the high level.
If the node K1 is at the high level, then the second NMOS transistor 24 is turned on. As the second NMOS transistor 24 is turned on, the potential of the node L1 is at the low level. As the potential of the node L1 is at the low level, the first NMOS transistor 23 is turned off. As the second PMOS transistor 22 maintains the turned-on state, the potential of the node B is at the high level.
If the potential of the node K1 is at the low level, then the second NMOS transistor 24 is turned off. As the second NMOS transistor 24 is turned off, the potential of the node L1 is at the high level. Accordingly, the high level signal is applied to the gate of the first NMOS transistor 23 connected to L1 so that the first NMOS transistor 23 is turned on. Here, as the second PMOS transistor 22 is always turned on, the power voltage Vdd is transmitted to the first NMOS transistor 23 through the second PMOS transistor 22 and the potential of the node B is at the low level. Consequently, the data output passing through the output buffer 5 becomes "0".
As illustrated in FIG. 3, in case the supply voltage is 5V, the size of the second PMOS transistor 22 and the first NMOS transistor 23 are controlled to have the optimal characteristics for detecting the data signal. According to the variation of the supply voltage, their size ratio is continuously varied.
The conventional semiconductor memory device has a problem as follows. If the supply voltage is varied, then the characteristic of the sense amplifier which should maintain the optimal characteristic is also varied. Therefore, the conventional memory device cannot be used with a wide range of supply voltages. As a result, the conventional memory device is not satisfactory to the various kinds of user requests for different supply voltages, and can cause an erroneous operation in an apparatus which employs a battery, i.e., an apparatus having variations in supply voltage.